The present invention relates to a multi-layer capacitor and method for manufacturing same; and more particularly, to a multi-layer capacitor including a plurality of laminated internal electrode layers having dielectric layers interposed therebetween forming a chip structure.
A multi-layer capacitor normally includes a plurality of laminated internal electrode layers having dielectric layers interposed therebetween, forming a chip structure. Edges of the internal electrode layers are alternately exposed to two opposing end surfaces of the chip. The edges of the internal electrode layers exposed to one of the two opposing surfaces of the chip are electrically connected to one of a pair of external electrodes; and, similarly, those of the internal electrode layers exposed to the other opposing surface of the chip are electrically connected to the other external electrode.
Such multi-layer capacitor includes a number of unit capacitors, which are connected in parallel to the pair of external electrodes. Each of the unit capacitors is formed by two adjacent internal electrode layers and a dielectric layer interposed therebetween. In principle, the electrostatic capacitance of such a multi-layer capacitor, i.e., a stack of vertically stacked unit capacitors, measured through the external electrodes is to be equal to the sum of the electrostatic capacitances of the individual unit capacitors. Thus, the capacitors are designed on such basis.
However, the overall electrostatic capacitance of the multi-layer capacitor actually measured through the external electrodes is lower than the sum of the electrostatic capacitances of the individual unit capacitors measured with the external electrodes removed. Moreover, the lowering of electrostatic capacitance varies from about 20 to 30% even within a same type of multi-layer capacitors. In particular, such lowering of electrostatic capacitance becomes ever severer in case of large capacitance type having a large number of thin dielectric layers.
The inventors of the present invention have studied the capacitance lowering problem of the prior art and conducted a series of experiments to rectify the problem; and have discovered that the residual stresses concentrated in a central region of the chip capacitor are largely responsible for the lowering the capacitance, although various other factors may also be attributable to such lowering of electrostatic capacitance. The manufacturing process of the chip type multi-layer capacitor includes the steps of forming an unsintered laminated structure by alternately stacking and compressing unsintered internal electrode layers and unsintered dielectric layers; and sintering the unsintered laminated structure so obtained. During the step of forming the laminated structure and the sintering step, varying stresses are generated at different locations within the body being processed, resulting in the residual stresses having different magnitudes and directions within the sintered chip. The residual stresses tend to be greater in the central region than the outer peripheral regions of the chip in the laminated direction; and parts of the dielectric layers having greater high residual stresses, when biased, are more vulnerable to the piezoelectric effect, leading to the lowering of the overall electrostatic capacitance.
It is, therefore, an object of the present invention to provide a multi-layer capacitor capable of securing a stable electrostatic capacitance close to a designed value and increasing a breakdown or withstanding voltage thereof.
In accordance with one aspect of the invention, there is provided a multi-layer capacitor including: a plurality of dielectric layers; a pair of external electrodes; and a multiplicity of internal electrode layers, each of the internal electrode layers being interposed between each pair of neighboring dielectric layers; one of said each pair of neighboring internal electrode layers being electrically connected to one of a pair of the external electrodes and the other one of said each pair of neighboring internal electrode layers being electrically connected to the other external electrode; and said each pair of neighboring internal electrode layers and the dielectric layer disposed therebetween forming a unit capacitor so that said multiplicity of internal electrode layers and dielectric layers therebetween constitute a stack of three or more vertically stacked unit capacitors, wherein the electrostatic capacitance of the unit capacitor located at a center of the stack is greater than those of the unit capacitors located at an upper end and a lower end of the stack.
In accordance with another aspect of the invention, there is provided a manufacturing method of the multi-layer capacitor including the steps of preparing green sheets; forming internal electrode layers on the green sheets; laminating and pressing the green sheets with the internal electrode layers formed thereon to thereby provide an unsintered stack of vertically stacked unit capacitors, the stack having two opposite end surfaces; sintering the unsintered stack; and forming external electrodes on the two opposite end surfaces, wherein the pressure employed in pressing one of the green sheets forming the unit capacitor located at a center region of the stack is higher than those employed in pressing the green sheets forming the unit capacitors located at a top end and a bottom end of the stack.
In accordance with still another aspect of the invention, there is provided a manufacturing method of the multi-layer capacitor including the steps of: preparing green sheets; forming internal electrode layers on the green sheets; laminating and compressing the green sheets with the internal electrode layers formed thereon to thereby provide an unsintered stack of vertically stacked unit capacitors, the stack having two opposite end surfaces; sintering the unsintered stack; and forming external electrodes on the two opposite end surfaces, wherein the dielectric constant of one of the green sheets forming the unit capacitor located at a center region of the stack is higher than those of the green sheets forming the unit capacitors located at a top end and a bottom end of the stack.